1. Field of the Invention
The present invention relates to a structure of a low-voltage channel write/erase flash memory cell and a fabricating method thereof. The present invention can apply the same voltage to a deep P-well and an N-well on an N-substrate by adding in a triple well architecture so that the leakage current capably generated can be reduced to minimum, thereby effectively reducing end voltages when performing the operation of erasing, simplifying the design complexity of a charge pump circuit required by the whole structure, and enhancing the operating efficiency.
2. Description of the Prior Art
Flash memories have been widely used in electronic products such as portable computers or communication apparatuses because of their non-volatile functions of electrically writing and erasing. The channel Fowler-Nordheim effect is generally exploited to operate the flash memory cell structure. Because the array structure thereof becomes denser and denser, the operation of each memory cell begins to influence one another. Therefore, the array density of the memory cell structure designed by using this effect has a certain limit. FIG. 1 is a cross-sectional view of the structure of a prior art channel write/erase flash memory cell. As shown in the figure, an N-well 12 is formed on a p-type substrate 10. An n-type region 15 is ion-implanted into the N-well 12 to be used as a drain. A p-type region 16 is also implanted into the N-well 12. Another p-type region 17 is ion-implanted below the type region 15. Because the implanted depth of the p-type region 17 is much larger than that of the p-type region 16, it can be used as a P-well. The p-type region 17 is connected to the p-type region 16. Moreover, an n-type region 18 is also ion-implanted at anther end of the p-type region 16 to be used as a source. A stacked gate G is disposed above the p-type region 16.
The operation of the above prior art will not be further described. According to this prior art, the source of the flash memory cell needs not to be at the opposite side of the drain thereof, i.e., it is a separate source. Each drain corresponds to a well. Therefore, when the density increases, the drawback of penetrating the source and the drain will not arise. Therefore, the integration can be increased.
However, when performing the operation of erasing, if a lower end voltage is to be used to reduce the burden of a charge pump circuit, a positive voltage originally applied to a word line and a source line grounding voltage will be respectively changed to a small positive voltage applied to the word line and a negative voltage applied to the source line. The negative voltage of the source line applied to the N-well 12 will generate a forward bias across a p-n junction between the N-well 12 and the grounded p-type substrate 10, thereby indirectly resulting in a leakage current IL so as to fail the action of erasing.
The primary object of the present invention is to provide a structure of a low-voltage channel write/erase flash memory cell and a fabricating method thereof, wherein a deep P-well and an N-well are formed on an N-substrate to form a triple well architecture to let the same voltage be applied to the deep P-well and the N-well on the N-substrate so that the two voltages can be balanced, thereby avoiding forward conduction of the p-n junction and thus reducing the leakage current.
The secondary object of the present invention is to provide a structure of a low-voltage channel write/erase flash memory cell and a fabricating method thereof. The present invention can apply the same voltage to a deep P-well and an N-well on an N-substrate by adding in a triple well architecture, thereby effectively reducing end voltages when performing the operation of erasing, simplifying the design complexity of a charge pump circuit required by the whole structure, and enhancing the operating efficiency.
Another object of the present invention is to provide a structure of a low-voltage channel write/erase flash memory cell and a fabricating method thereof, which can reduce the program disturb generated when performing the operation of programming.
To accomplish the above objects, the present invention provides a structure of a low-voltage channel write/erase flash memory cell, which comprises mainly an N-substrate, a deep P-well formed on the substrate, an N-well formed on the deep P-well, and a stacked gate disposed above the N-well. A deep p-type region and a shallow p-type region are ion-implanted at predetermined positions in the N-well. An n-type region is ion-implanted in the deep p-type region to be used as a drain. Another n-type region is also ion-implanted at one side of the shallow p-type region to be used as a source. Because the present invention is operated at low voltages, the same voltage can be applied to the deep P-well and the N-well on the N-substrate to let the leakage current possibly generated be reduced to minimum.
The present invention also provides a fabricating method of the structure of a low-voltage channel write/erase flash memory cell. The proposed fabricating method comprises mainly the following steps: ion-implanting a deep P-well in an N-substrate; ion-implanting an N-well in the deep P-well; ion-implanting a shallow p-type region on the surface of the N-well; growing a tunnel oxide on the N-well and depositing a poly-Si layer; etching the tunnel oxide and the poly-Si layer; depositing an oxide-nitride-oxide (ONO) film on the etched tunnel oxide and the etched poly-Si layer; depositing a poly-Si layer on the ONO film; etching all the grown layers and the deposited layers on the N-well to form a rectangular stacked layer (two sides of the rectangular stacked layer being the exposed N-well); ion-implanting a deep p-type region in the N-well and disposed at one side of the rectangular stacked layer; and ion-implanting a plurality of n-type regions in the N-well and disposed at two sides the rectangular stacked layer.
These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the multiple figures and drawings.